SAP‑1 Architecture Based 8‑bit Computer 

This project implements the classical SAP‑1 (Simple‑As‑Possible) computer as a complete 8‑bit microprocessor in Proteus. The build covers the full fetch decode execute pipeline, a programmable clock system, memory and register file, ALU, instruction register and controller/sequencer, display subsystems, and auxiliary modules. The goal was to realize and optimize a working minimalist computer to understand microprocessor internals end‑to‑end.

Clock & Timing System

A dual‑mode clock pulse generator supports both automatic and manual stepping using 555‑timer–based multivibrators: an astable (free‑running) clock for continuous operation and a monostable for debounced single‑step execution. A bistable multivibrator acts as the mode selector (Auto/Manual), with a small combinational block implementing the final selection logic. A full clock circuit integrates these units to drive the SAP‑1 T‑state sequencer.

Core Datapath Modules

• Program Counter (4‑bit asynchronous up‑counter): Feeds sequential addresses to RAM; CE increments the counter after an instruction cycle.
• MAR (Memory Address Register, 4‑bit PIPO using SR FFs): MI selects Shift/Load behavior; outputs the active address during RUN.
• Address Selector: Chooses between manual program state and MAR‑driven run state for the 4‑bit address bus.
• Accumulator (8‑bit PIPO): AI loads from bus; AO (via tri‑state buffers) places accumulator contents on the system bus and directly to the ALU.
• B‑Register (8‑bit PIPO): BI loads from bus and feeds the ALU.
• Output Register (8‑bit PIPO): OI latches accumulator data for display; feeds Binary→BCD display path.
• RAM (16×8): Built bottom‑up from SR‑latch primitives (IC‑4043) → 4‑bit → 8‑bit blocks, then arranged as 16×8 with a 4→16 decoder and RO tri‑state outputs.

Arithmetic & Logic Unit (ALU)

The ALU performs 8‑bit addition and subtraction using cascaded 4‑bit adders. Subtraction uses a controllable inverter/X‑NOR network to form 2’s complement on B when SU is asserted, with EO enabling ALU results onto the system bus.

Instruction Path & Control

• Instruction Register (8‑bit PIPO): II loads opcode+operand from bus; the upper nibble goes directly to the controller, the lower nibble (via IO) returns to the bus→MAR.
• Macro‑Instructions: LDA, ADD, SUB, OUT, HLT decoded from the IR upper nibble.
• Controller/Sequencer: A T‑state counter (T1–T5) with reset/skip (SJ) generates micro‑instructions per cycle; HLT halts by gating the clock.

Display & Auxiliary Modules

• Binary→BCD Converter: Shift‑add‑3 method with C‑blocks; K‑map–derived boolean equations implement the add‑3 decision.
• T‑State Display: Combinational decoder shows current T‑state (T1–T5).
• Sign Indicator Path: C and D registers capture ALU sum and B‑register value; a comparator drives a sign display (negative indicator) based on their relation.
• Reset Circuit: SPDT‑based global active‑high clear to initialize all modules.

Outcomes, Limitations, and Future Work

Outcomes: A working SAP‑1 8‑bit computer in Proteus demonstrating complete fetch‑decode‑execute behavior across LDA/ADD/SUB/OUT/HLT, with debounced single‑step, macro/micro control, ALU arithmetic, RAM read/write, and live state displays.
Limitations: Simulation‑only build (no hardware realization); sensitivity to specific logic IC models (e.g., NOT 7406 behavior across modules).
Future Work: Reduce T‑states from 5→4; gate‑count optimization; replace large PLDs with EEPROM‑based control; full hardware implementation.